A Principal FPGA Design Engineer position in Pasadena, CA recently opened up to support JPL/NASA. In this role you will lead the planning and execution of highly sophisticated and unique electronics systems with laboratory wide impact. To be considered for this role, you must have a Bachelor’s degree in Electronics, Electrical, or Computer Engineering or related discipline with typically a minimum of 12 years of related experience. You must also be a US Citizen or Permanent Resident.
Location: Pasadena, CA 91109
Position: Electrical Engineer IV
Pay Rate: $64.15/hr – 98.60/hr DOE
Duration: 24 months
Flexible work schedule: Hybrid 9/80
We do offer PTO, holidays, 401k, medical, dental, and vision
Responsibilities:
As a principal level FPGA Design Engineer, you will lead the planning and execution of highly sophisticated and unique electronics systems with Laboratory wide impact.
ESSENTIAL DUTIES AND RESPONSIBILITIES Include the following. Other duties may be assigned:
- Verify that FPGA/ASIC designs are flight worthy
- Improve FPGA verification flow
- Improve verifying hardware resilience
- Mentor junior engineers
Requirements:
- Bachelor’s degree in Electronics, Electrical, or Computer Engineering or related discipline with typically a minimum of 12 years of related experience; Master’s in similar disciplines with a minimum of 10 years of related experience; or PhD in similar disciplines with a minimum of 8 years of related experience
- Expert in architecting, designing, and implementing Block and System-level UVM/UVMF constrained random verification environments.
- Expert coding in System Verilog
- Expert creating a verification plan and functional coverage matrix from requirements and design specification.
- Demonstrated experience leading a verification team and presenting in design reviews
- Must have experience through an FPGA/ASIC full life cycle from initial concept to burn review/tapeout.
- Success infusing new verification technologies and methodologies
- Skillfully handles fast pace and dynamic product development environment
- Excellent written/verbal communication skills
Desired Skills:
- Experience with Mentor Questa Verification tool suite and Questa Verification IP
- Experience in bus standards protocol such as: SpaceWire, PCI, MILSTD-1553, CAN, and Ethernet
- Experience integrating MATLAB/Simulink models into a UVM verification environment
- Experience with SVA and static formal model checking
- Experience with continuous integration (Jenkins)
- Experience with configuration management (Github)
About our client:
Our client is a research and development lab federally funded by NASA and managed by Caltech. Manages many of NASA's robotic missions exploring Earth, the solar system, and our universe.
About APR:
Since 1980 APR Consulting, Inc. has provided professional recruiting and contingent workforce solutions to a diverse mix of clients, industries, and skill sets nationwide.
We are an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law.
Don't miss out on this amazing opportunity! If you feel your experience is a match for this position, please apply today and join our team. We look forward to working with you!
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